In the fabrication of integrated circuits it is often necessary to form a large number of transistors on a single chip. These transistors are interconnected to form logic gates, flip-flops, memory cells and a wide variety of other devices. In most static logic, a high transistor channel conductance is desirable to accomplish high speed operation. In some circuits such as static random access memories (SRAM) for example, however, a low conductivity transistor is desirable to achieve stable write operation with a wide process margin.
One common way to accomplish the goal of having both high and low conductivity transistors on the same chip is to design the entire layout of the chip for each application. With a custom layout, transistors of different sizes can be easily implemented. The disadvantage, however, is that all the levels of the multilevel device must be designed for each particular implementation.
On the other hand, a gate array is an array of transistor circuits which utilize the same base cell for many different applications. In this configuration, only the final interconnect levels of the multilevel device are specifically designed for any given application. The initial levels, known as the base cell, are the same for each implementation. This methodology makes it more difficult than customized layouts to have transistors of different sizes since the locations of the various conductance transistors will vary from application to application.
When using gate arrays, one my build transistors of identical sizes and design the circuitry accordingly. To satisfy the requirement of gates with varying driveability, more than one transistor may be connected in a manner such that the configurations of multiple transistors will appear to have varying conductances. These methods, however, require more transistors per application than customized layouts and it in turn will require more area on the chip.
Another method for designing gate arrays is to include more than one size of transistor in the base cell pattern. In this case, the final configuration can be connected to utilize whichever size transistor is required for the current application. Once again, however, there will be many transistors which will not be used. In addition, it is desirable to avoid long connections of transistors to help enhance final speed.
Accordingly, improvements which overcome any or all of the problems are presently desirable.